In recent years, a technique which is supposed to improve performance of a semiconductor device and to reduce parasitic capacitance has been developed. As the technique to reduce the parasitic capacitance, there is a silicon on sapphire (SOS) structure. As a method of forming the SOS structure, there is a technique disclosed in Japanese Unexamined Patent Application Publication No. 2003-31781, for example. In addition, as a method of bonding a substrate made of a different material, there is a technique described in Japanese Unexamined Patent Application Publication No. 2004-343369, for example.